Staff Serdes Physical Implementation Engineer

Description:

In this role, you will be responsible for the Physical Implementation of high speed interface IPs and test-chips, driving all aspects from RTL to GDS including timing and physical sign-off. You will work in close interaction and collaborative team work with multiple functional groups (front end digital, analog design and layout, CAD) and the product team.

As a Staff SerDes Physical Implementation Engineer, the successful candidate will work on a variety of advanced SERDES developments including the latest 56/112/224G standards. The digital implementation organization is seeking a motivated person responsible for the physical implementation of complex IPs and testchips across multiple process technologies with a specific focus on very advanced high speed SERDES platforms.

The successful candidate will have the following: 10 + years of digital or physical design experience with recent contribution to project tape-outs, as a technical driver and/or project head.
 

• Intimate understanding of the full design cycle from RTL to GDSII, including chip level.
• Experience with advanced FinFET nodes, TSMC 16 nanometer or below, including low-power design techniques
• A solid engineering understanding of the underlying concepts of digital design and architecture, implementation flows and physical and timing signoff
• Development of timing constraints and design architectures to ensure on-time delivery, and to meet or exceed power and area targets
• Excellent communication skills, ability to think and communicate at different levels of abstraction, with peer groups as well as customers.
• Methodology guided with excellent software and scripting skills (Perl, Tcl, Python); understanding of CAD automation methods.
• Solid understanding of the challenges inherent in analog/digital interfaces.
• Autonomous, and able to cope with interrupts.
   

Requirements
 

• MSEE and 8+ years or BSEE and 10+ years
• Previous project leadership experience
• Solid understanding of digital / mixed signal verification flows and SOC integration challenges.
• Ability to travel internationally as required.