Soc Design Verification Engineer
Description:
🚀 Hiring: SoC Design Verification Engineer | Senior DV Engineer
📍 Location: Cambridge & Bristol, UK(Hybrid – Minimum 3 days/week onsite)
💼 Contract: 6 Months
🎯 Experience: 5–20 Years
⚡ Immediate Hiring | Urgent Requirement
🔹 Key Skills Required
SystemVerilog & UVM
SoC / Subsystem Functional Verification
UVM Testbench Reuse, Enhancement & Debugging
Processor-Based C Test Development & Verification
RTL Simulation & Debugging
Functional Coverage & Coverage Closure
Regression Execution & Failure Analysis
ARM-Based SoC Architecture
Gate-Level Simulation
Python / Perl / Shell Scripting
| Organization | ST Global Tech |
| Industry | Engineering Jobs |
| Occupational Category | SoC Design Verification Engineer |
| Job Location | Cambridge, ON, Canada |
| Shift Type | Morning |
| Job Type | Full Time |
| Gender | No Preference |
| Career Level | Experienced Professional |
| Experience | 5 Years |
| Posted at | 2026-11-09 12:55 pm |
| Expires on | 2026-12-24 |