Senior Design Engineer

Description:

The Timing and Communication Group (TCG) at Microchip is actively seeking an analog design engineer. The responsibility spans a wide range of activities such as the design, simulation and validation of analog integrated circuits (ICs). The products are usually mixed signal SOC designs.

The Analog team develops critical IP blocks used in the TCG timing products. These circuits include multi-GHz PLL circuits, high speed digital circuits, MEMS drivers and high-speed performance IO pads.

As an analog Senior Design Engineer and as part of the Analog IP team the individual will:

• Work with analog design lead and architects to design specific analog IP blocks
• Simulate analog circuits across process corners and operating conditions
• Models design blocks to be included in top level mixed signal simulations
• Block-level validation of process silicon devices and system-level lab evaluation
   

Requirements/Qualifications
 

• Master’s degree or PhD in electrical engineering
• Minimum of 5 years of direct experience working on analog and mixed-signal circuits
• Experience in high-speed and analog circuit design including the following: ADCs, DACs, Filters, PLLs, DLLs, and high-speed I/Os
• Strong fundamentals of circuit theory, design, and layout
• Hands-on experience in scripting and automation using skill language, python, Perl and tcl
• Strong knowledge in Cadence IC design flow and tools
• Expertise in the system design of mixed signal circuits is preferred
• Strong knowledgeable in Verilog-A for analog behavioral modeling and simulation
• Good communication and teamwork skills, and experience working with multi-site teams, are desirable