Memory Layout Engineer

Description:

"Memory Layout Engineer (5-8 years’ experience)

This role is for a seasoned memory layout engineer with 5-8 years of experience to lead the design and development of high-performance memory blocks for integrated circuits (ICs). You will be a technical expert responsible for creating innovative memory layouts that push the boundaries of performance, power efficiency, and area optimisation.

Responsibilities

• Lead the design and development of memory layouts for complex ICs, including:

• High-density SRAM memories

• Specialty memory blocks (e.g., ROM, CAM)

• Define memory architecture and sub-block specifications

• Develop and implement advanced layout techniques for low-power, high-speed memory design

• Collaborate with design and verification teams to ensure seamless integration

• Mentor junior engineers and provide technical guidance

• Stay up-to-date on the latest memory design trends and technologies

• Perform comprehensive physical verification using DRC, LVS, and other tools

• Drive Design for Manufacturability (DFM) and Design for Yield (DFY) initiatives

• Analyze layouts for potential power integrity and signal integrity issues

• May involve scripting automation for layout tasks using languages like PERL, Shell, TCL, or Skill

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field

• 5-8 years of experience in advanced memory layout design

• In-depth knowledge of memory compiler architectures, sub-blocks, and functionalities

• Proven expertise with memory layout tools like Cadence Virtuoso, Calibre, and Assura

• Extensive experience with low-power, high-performance, and high-density memory design across various leading technology nodes (e.g. 3nm 5nm 7nm FinFET)

• Solid understanding of Design for Manufacturability (DFM) and Design for Yield (DFY) principles

• Strong leadership, communication, and teamwork skills

• Ability to manage multiple projects and meet deadlines effectively

Preferred Skills

• Experience with emerging memory technologies (e.g., MRAM, ReRAM)

• Experience with advanced place and route techniques for memory layouts

• Experience with memory verification methodologies and automation tools

• Scripting proficiency for layout automation and data analysis