Digital Design Engineering Intern

Description:

The following are examples of tasks that our past interns were involved in:
 

• RTL coding, analog block modeling, and writing testbenches in SystemVerilog.
• Defining synthesis design constraints and resolving STA issues.
• Defining Clock/Reset domain crossing design constraints.
• Debugging RTL and gate-level simulation failures.
   

Skill Requirements
 

• Proficient in languages such as C, Verilog, SystemVerilog, Python and Perl.
• Excellent knowledge of digital design theory.
• Motivated, eager, and interested in ASIC digital design.
• Persistence and determination.